IBM Research, in collaboration with Albany Research Alliance partner Samsung, has developed a breakthrough semiconductor called Vertical-Transport Nanosheet Field Effect Transistor, or VTFET, which could prolong Moore’s Law for several decades. The team successfully implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow.

Gordon Moore first predicted in 1965 that roughly every two years, the number of transistors and other components in a dense integrated circuit would double and double the speed and capacity of computers. Today, however, the number of transistors that can be crammed into one chip has just about reached its limit.

Despite this, computing systems have a long way to go. From road safety to drug discovery and advanced manufacturing, dynamic AI systems will profoundly impact our lives, requiring bigger and more powerful chips in the future. So, As Moore predicted, we’ll need chips with up to 100 billion transistors to maintain Moore’s predictions in terms of speed and computing power.

Moore’s Law reimagined within the framework of VTFET

In today’s semiconductor industries, the dominant chip technology is lateral-transport field-effect transistors (FETs), such as the finFET (named for the way silicon’s body resembles a fish’s back fin). In VTFET, transistor layers are perpendicular to the silicon wafer, and there is direct current flow vertically to the wafer surface. By using this technology, scaling can be increased by relaxing physical constraints on transistor gate length, spacer thickness, and contract size, each of which can be optimized for either performance or energy efficiency. For example, VTFET could be used to provide two times the performance of up to 85 per cent reduction in energy use, compared to the scaled finFET alternative.

Additionally, VTFET is a better alternative than nanosheet technology in CMOS semiconductor design in terms of scale. Another key VTFET feature is using STI for adjacent circuit isolation to achieve a Zero-Diffusion Break (ZDB) isolation, with no loss of active-gate pitches. By comparison, the density of lateral-transport FET circuitry is affected by double or single-diffusion breaks required for circuit isolation, affecting the ability to shrink the technology further.

An image of FET layers arranged horizontally on a wafer with Dummy isolation gates, shown in blue, which are required to isolate adjacent circuits which waste space.

VTFET’s Possibilities:

With this breakthrough, the semiconductor industry could continue its relentless quest to make significant improvements, including:

• An architecture that may enable semiconductor devices to scale further than nanosheets.
• Instead of needing to charge a cell phone every few days, one could go over a week without charging.
• Data encryption and crypto mining operations require a lot of energy to operate, but their carbon footprint could be reduced significantly.
• IoT and edge devices will become more energy-efficient, enabling them to be used in a range of environments, including autonomous vehicles, 

As far back as a decade ago, we could already see that lateral architecture would hit scaling limits at aggressive gate pitches. Practically, each of the device components was nearing scaling limits that could break those barriers and may produce a competitive device for the technologies.