Archives for chip design
‘We were able to generate 83% smaller tactical ECO patches using the new Cadence Conformal AI ECO flows.’
The post Cadence Launches Conformal AI Studio, Improves SoC Productivity by 10x appeared first on AIM.
AI-based tool for FPGA designers showed about 5 times (more in many cases) improvement in the output by senior engineers
The post India’s Chip Design Workforce Under Massive AI Threat appeared first on Analytics India Magazine.
At least in the next five years, while we will not witness real intelligence, enabling reliable hardware will be a crucial aspect of achieving that.
The post ChatGPT-like Models are a Threat to VLSI Design appeared first on Analytics India Magazine.