Despite the growing voices declaring a possible end of Moore’s law, the semiconductor industry is still scaling chips along the historical trajectory. At the 68th Annual IEEE International Electron Devices Meeting (IEDM), TSMC spoke about its 3nm node technology, the class of which includes the original base N3 (N3B) node and the enhanced variant (N3E). 

However, what was left out of the conversation at the event is that while the logical circuits have been scaling well, SRAM, the memory chip is unable to keep pace. For instance, TSMC’s N3 consists of an SRAM bitcell size of 0.0199µm^², only ~5% smaller than N5, the 5nm node technology, which is 0.021 µm^². And the N3E features 0.021 µm^² SRAM bitcell, meaning it is the same size as N5. 

But, as Wikichip reports, the scaling crisis is not limited to TSMC. Instead, it is a phenomenon spread industry-wide (see graph). 

SRAM provides on-chip cache memory for microprocessors in PCs and mobile devices, often taking up much space on the chip. The memory cells allow cramming multiple functions onto a single chip without compromising on power and performance. Thus, the slowdown in SRAM scaling could hamper the amount of cache memory size included in processors. This would, in turn, affect the PC and smartphone pricing as well. 

The cache is particularly important to processors since it is faster than typical main DRAM memory by an order of magnitude and helps processors speed up operation. On the flip side, it is usually the toughest part to scale. Kaizad Mistry, corporate vice president at Intel, in speaking about SRAM, told Semiconductor Engineering back in 2013, “It is important to scale this component of the technology by close to 0.5x from one generation to the next. The key limiter to scaling the SRAM is to minimise transistor variation, which can make the SRAM cell unstable.” In the graph above, we can see the case of Intel alone slowing to 0.6-0.7x scaling from 0.5-0.6x scaling for their Intel 4 process. 

Issues with FinFET transistors

Both Samsung and TSMC, considered to be the only foundries (along with Intel, maybe) capable of producing advanced node processes, use FinFET transistors for their 7nm and 5nm technologies. FinFETs are 3D-like structures with better performance and lower leakage than traditional planar transistors. But, with FinFETs, there are some evident limitations. 

The advanced node processes—namely 5nm and above—are going through what is called the “ageing problems”. Firstly, densely packed devices are highly susceptible to self-heating due to higher speeds, especially in the case of 2.5D and 3D designs. And secondly, the devices today are operating around 0.6 to 0.7 volts at 3nm, because of which the electric fields have increased, which can, in turn, cause the devices to break down. Thus, reliability issues are a major concern when it comes to FinFET models. 

Further, as Synopsys’ Haran Thanikasalam notes, “FinFETs can be multi-threshold devices, so when you have the entire gamut of threshold voltage being used in a single IP, we have so many problems because every single device will go in a different direction.”

A mammoth task lies in front of SRAM of playing catchup to the scaling abilities of logical circuits, which might put the trajectory of Moore’s law on hold. However, scaling to 3nm and 2nm is not necessarily a failed cause. “The industry will find new ways to increase cache memory by potentially splitting the functionality across chiplets. 2nm will have the benefit of GAA transistor architecture which could potentially help improve the SRAM density,” said Kundojjala. 

TSMC 3nm versus Samsung 3nm

To solve the issue, Samsung recently announced that it would transition to a new transistor architecture called the nanosheet FET for the 3nm process. Samsung’s proprietary GAA technology, known as Multi-Bridge-Channel (MBCFET), defies some of the limitations associated with FinFET. The 3nm GAA technology allows Samsung to adjust the channel width so it can utilise nanosheets with wider channels than other GAA technologies to optimise power usage and performance to meet various customer needs.  

The design flexibility of GAA is highly valuable for Design Technology Co-Optimisation (DTCO) as it is beneficial in areas of Power, Performance, and Area (PPA). For example, the second-generation 3nm process trumps the 5nm process by reducing power consumption by up to 50%, improving performance by 30% and reducing area by 35%. 

Contrary to Samsung, TSMC’s 3nm process technology would stick to FinFET transistors and instead rely on “innovative features” to achieve the full-node scaling. Amongst the additional features include the finflex technology, which allows designers to select a technology between three configurations that fares well with their needs. Each of the three configurations is a tradeoff between power, performance, and area. 

Road ahead

General-purpose processors, graphics chips, and application processors for smartphones have huge caches, even when it is said to be inefficient in fetching data from memory, especially for AI and ML workloads. Some notable examples include AMD’s Ryzen 9 7950X carries 81MB of cache in total, and Nvidia’s AD102, which uses at least 123MB of SRAM.

Anton Shilov, writing for Tom’s Hardware, resonates with Kundojjala while saying that the slowdown of SRAM scaling could be mitigated by “going for a multi-chiplet design and disaggregating larger caches into separate dies made on a cheaper node”. AMD has been doing this with its 3D V-Cache, which allows them to stack cache vertically on a processor. 

Moreover, as Wikichip puts across, some emerging technologies, such as MRAM, FeRAM, NRAM, RRAM, STT-RAM, and PCM, provide unique tradeoffs like higher density at lower read/write specifications, non-volatility capabilities, lower read-write cycle capabilities, or lower power at potentially lower density or speeds. 

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